From: Matan Ziv-Av (matan@svgalib.org)
Date: Tue 30 Apr 2002 - 12:45:12 IDT
On Mon, 29 Apr 2002, Andrea Mazzoleni wrote:
> The PLL N divider is sometimes computed incorrectly.
>
> For example with this modeline :
> 21.2784 416 424 488 520 312 318 320 341 -hsync -vsync doublescan
>
> the values computed by the NV3ClockSelect function are :
> m=13 n=309 p=4
> There N is out of the 8 bit allowed range.
Thanks. I fixed the problem by using the newer clock calculation routine
from nv driver in XFree86. It actually also had this problem, but only
for high clock frequencies (>246MHz).
--
Matan Ziv-Av. matan@svgalib.org
------------------------------------------------------------------
Unsubscribe: To: listbot@svgalib.org
Body: unsubscribe linux-svgalib
This archive was generated by hypermail 2.1.4 : Wed 21 Jan 2004 - 22:10:24 IST